Senior AMS Verification Engineer

Job description

A market leader in the development of MEMS based silicon timing system solutions in the Netherlands is looking to hire a Senior AMS Verification Engineer with strong skills in Verilog modelling. An attractive salary package will be offered to the successful candidate including 30% tax ruling and relocation. Visa can be provided for the successful candidate if needed.

Responsibilities:

• Develop functional models for analog and mixed-signal circuits using Verilog or similar language
• Write verification specifications based on requited test cases
• Top level digital verification
• Develop test benches in Verilog or similar languages/environments to verify the top level functions of full chips
• Run verification test benches and communicate results to the team for any fixes/improvements

Qualifications & Requirements:

• University Degree or higher in electrical engineering
• Experience with analog and digital circuit design (Analog Mixed Signal)
• Understanding of Analog schematic and experience with Cadence Virtuoso
• Scripting languages such as Perl / Python
• Experience with digital design languages, such as Verilog/SystemVerilog, skills in Verilog-AMS are a plus,
• Understanding of mixed signal designs verification flow
• Strong communication skills in English

For more information and to apply, please clock APPLY NOW to speak with Ane!