Mask/RFIC Layout Engineer


DISYS - Digital Intelligence Systems, LLC

2020-09-23 17:39:33

Job location Cupertino, California, United States

Job type: fulltime

Job industry: I.T. & Communications

Job description

Job Title: Mask Layout Engineer

Locations: San Jose, CA || Austin, TX || Colorado || Florida

Complete Description:

  • Responsible for mask layout of analog designs for integration into a System-on- Chip (SoC).
  • Independently interact with circuit designer or layout lead to understand layout requirements to meet circuit performance requirements.
  • Assess, plan, and execute as required to meet schedule deadlines and communicate potential problems to circuit designer or layout lead.
  • Work with other custom analog layout designers and ensure quality of work is meeting standards required by circuit design or layout lead.

Skills:

  • MacOS
  • iOS
  • Bachelor's degree or foreign equivalent in Electrical Engineering, Electronic Engineering, or related field and 6+ years of experience in the job offered or related occupation.
  • Alternatively, employer will accept a Master's degree or foreign equivalent Electrical Engineering, Electronic Engineering, or related field and 3 years of progressive, post-baccalaureate experience in the job offered or related occupation.

3 years of experience with each of the following skills is required:

  • Layout design of tight matching, low noise, and low power analog blocks, resistors, capacitors, pad IOs, and ESD structures;
  • IR drop, RC delay, electro migration, self-heating, and cross capacitance;
  • CALIBRE DRC, ERC, and LVS reports;
  • Analog/mixed-signal layout design of SubMicron CMOS circuits;
  • Recognizing failure prone circuit and layout structures; and
  • Analog and DFM best practices.

Job Title: RFIC Layout Engineer

Locations: San Jose, CA || Austin, TX || Colorado || Florida

Notes: 7nm exp is a must along with Strong Analog experience.

Complete Description:

In this role, you will work closely with the RFIC design team to layout and verify custom RF and analog IP for complex SoC products.

Key Qualifications

  • Experience in custom RF/analog layout with extensive knowledge of deep sub-micron CMOS (40nm, 28nm, FinFET, etc.)
  • Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing
  • Solid understanding of RC delay, electromigration, and coupling
  • Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.
  • High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc.
  • Knowledge of CADENCE layout tools
  • Excellent communication skills and able to work with cross-functional teams
  • You would also have the following, if you're more experienced:
  • Capability to lead other layout engineers for top-level integration
  • Ability to recognize failure prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems
  • Scripting skills in PERL or SKILL are a plus, but not required

As a RF layout engineer, you will be responsible for

  • Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.
  • Block level and top-level layout through full verification flow including extraction, DRC, LVS, and DFM checking
  • Co-work with designers on block level and top-level floorplanning
  • Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling
  • Top-level layout integration and verification, schedule management

The end client is unable to sponsor or transfer visas for this position; all parties authorized to work in the US without sponsorship are encouraged to apply.

- provided by Dice

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