ASIC RTL Designer


Radiansys, Inc.

2019-01-11 14:07:38

Job location Santa Clara, California, United States

Job type: all

Job industry: I.T. & Communications

Job description

This position is for our client located in Santa Clara, CA.

Responsibilities:

Block Level RTL design and verification for Ethernet application

Documentation on RTL design details

Working with DV on functional debugging

Required Qualifications:

2+ Years ASIC RTL experience with Verilog, and/or SystemVerilog

Experience in hardware architecture design, micro-architecture

Extensive experience on Ethernet protocols

- provided by Dice ("verilog" OR "systemverilog" OR "sysverilog" OR "asic rtl" OR "rtl designer")

Inform a friend!

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